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publication order number: fan3268/d ? 2009 semiconductor components industries, llc. september-2017, rev. 2 fan32 68 ? 2 a low - voltage pmos - nmos bridge driver fan32 68 2 a low - voltage pmos-nmos bridge driver features ? 4.5 v to 18 v operating range ? drives high - side pmos and low - side nmos in motor control or buck step - down applications ? inverting channel b bias es high - side pmos device o ff (with internal 100 k resistor) when v dd is below uvlo threshold ? ttl i nput t hresholds ? 2.4 a s ink / 1.6 a s ource at v out =6 v ? i nternal r esistors t urn d river o ff if n o inputs ? millerdrive? technology ? 8- lead soic package ? rated from ? 40c to +1 25 c ambient ? automotive qualified to aec - q100 (f085 version) applications ? motor control with pmos / nmos half - bridge configuration ? buck converters with high - side pmos d evice ; 100% d uty c ycle o peration p ossible ? logic -c ontrolled load circuits with high - side pmos s witch ? automotive - qualified systems (f085 version) descript ion the fan 3268 d ual 2 a g ate driver is optimized to drive a high - side p - channel mosfet and a low - side n- channel mosfet in motor control applications operating from a voltage rail up to 18 v. the driver has ttl i nput thresholds and provides buffer and level translation function s from logic inputs . internal circuitry provides an under - voltage lockout function that prevents the output switching devices from operating if the v dd supply voltage is bel ow the operating level. internal 100 k resistors bias the non- inverting output low and the inverting output to v dd to keep the external mosfets off during startup intervals when logic control signals may not be present . the fan 3268 driver incorporate s millerdrive? architecture for the fina l output stage. this bipolar - mosfet combination provides high current during the miller plateau stage of the mosfet turn - on / turn- off process to minimize switching loss, while providing rail - to - rail voltage swing and reverse current capability. the fan 326 8 has two independent enable pin s that default to on if not connected . if the enable pin for non - inverting channel a is pulled low , outa is forced low ; if the enable pin for inverting channel b is pulled low , outb is forced high. i f an input is left unconnected , internal resistors bias the inputs such that the external mosfets are off. related resources an- 6069 ? application review and comparative evaluation of low - side gate drive rs motor c byp 1 2 3 vdd gnd enb 4 8 7 6 5 b a ena +vrail (4.5?18v) controller fan3268 figure 1. typical motor drive application
www.onsemi.com 2 fan32 68 ? 2 a low - voltage pmos - nmos bridge driver ordering information part number logic input threshold packing method fan3268tmx non - inverting channel and inverting channel + dual enables ttl 2,500 units on tape & reel fan3268tmx-f085 (1) no n - inverting channel and inverting channel + dual enables ttl 2,500 units on tape & reel 1. qualified to aec - q100 p ackage outline 2 3 8 6 1 4 7 5 ena ina gnd inb enb outa vdd outb figure 2. pin configuration (top view) thermal characteristics ( 2 ) package 8- pin small outline integrated circuit (soic) 40 31 89 43 3 c/w notes: 2. estimates derived from thermal simulation; actual values depend on the application. 3. theta_jl ( jl ): thermal resistance between the semiconductor junction and the bottom surface of all the leads (including any thermal pad) that are typically soldered to a pcb. 4. theta_jt ( jt ): thermal resistance between the semiconductor junction and the top surface of the package, assuming it is held at a uniform temperature by a top - side heatsink. 5. theta_ja ( ja ): thermal resistance between junction and ambient, dependent on the pcb design , heat sinking, and airflow . t he value given is for natural convection with no heatsink using a 2s2p board, as specified in jedec standards jesd51 - 2, jesd51 - 5, and jesd51 -7 , as appropriate . 6. p si _jb ( jb ): thermal characterization parameter providing correlation between semiconductor junction temperature and an appl ication circuit board reference point for the thermal environment defined in note 5 . for the soic - 8 package, the boar d r eference is defined as the pcb copper adjacent to pin 6 . 7. p si _jt ( jt ): thermal characterization parameter providing correlation between the semiconductor junction temperatur e and t he center of the top of the package for the thermal environment defined in note 5 .
fan32 68 ? 2 a low - voltage pmos - nmos bridge driver pin definitions pin# name description 1 ena enable input for channel a . pull pin low to inhibit driver a. ena has ttl thresholds. 8 enb enable input for channel b . pull pin low to inhibit driver b. enb has ttl thresholds. 3 gnd ground . common ground reference for input and output circuits. 2 ina input to channel a . 4 inb input to channel b . 7 outa gate drive output a : held low unless required input(s) are present and v dd is above the uvlo threshold. 5 outb gate drive output b (inverted from the input): held high unless required input is present and v dd is above uvlo threshold. 6 vdd supply voltage . provides power to the ic. output logic fan3268 (c hannel a) fan 3268 (c hannel b) ena ina outa enb inb outb 0 0 ( 8 ) 0 0 0 ( 8 ) 1 0 1 0 0 1 1 1 ( 8 ) 0 ( 8 ) 0 1 ( 8 ) 0 ( 8 ) 1 1 ( 8 ) 1 1 1 ( 8 ) 1 0 note: 8. default input signal if no external connection is made . www.onsemi.com 3
fan32 68 ? 2 a low - voltage pmos - nmos bridge driver bl ock diagram 6 vdd 7 v dd _ ok 5 ina 2 100 k ? ena 1 gnd 3 vdd uvlo 100 k ? 8 vdd enb inb 4 outa 100 k ? 100 k ? 100 k ? outb 100 k ? fi gure 3. block diagram www.onsemi.com 4
fan32 68 ? 2 a low - voltage pmos - nmos bridge driver absolute maximum ratings stresses exceeding the absolute maximum ratings may damage the device. the device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. in addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. the absolute maximum ratings are stress ratings only. symbol parameter min. max. unit v dd vdd to gnd - 0.3 20.0 v v en ena , enb to gnd gnd - 0.3 v dd + 0.3 v v in ina, inb to gnd gnd - 0.3 v dd + 0.3 v v out outa , outb to gnd gnd - 0.3 v dd + 0.3 v t l lead soldering temperature (10 seconds) +260 oc t j junction temperature -55 +150 oc t stg storage temperature -65 +150 oc symbol parameter min. max . unit v dd supply voltage range 4.5 18.0 v v en enable voltage ( ena , enb ) 0 v dd v v in input voltage ( ina, inb ) 0 v dd v t a operating ambient temperature -40 +125 oc www.onsemi.com 5
fan32 68 ? 2 a low - voltage pmos - nmos bridge driver electrical characteristics unless otherwise noted, v dd =12 v and t j =- 40c to + 12 5c. currents are defined as positive into the device and negative out of the device. symbol parameter conditions min. typ. max. unit supply v dd operating range 4 .5 18. 0 v i dd supply current inputs / en not connected 0. 75 1.2 0 ma fan3268t uvlo v on device turn - on voltage ina=ena=v dd , inb=enb=0 v 3.5 3.9 4.3 v v off device turn - off voltage ina=ena=v dd , inb=enb=0 v 3.3 3.7 4.1 v fan3268tmx_f085 uvlo (automotive - qualified versions) v on device turn - on voltage ( 12) ina=ena=v dd , inb=enb=0 v 3. 3 3.9 4. 5 v v off device turn - off voltage ( 12) ina=ena=v dd , inb=enb=0 v 3. 1 3.7 4. 3 v input (9) fan3268t v il inx logic low threshold 0 .8 1.2 v v ih i nx logic high threshold 1 .6 2.0 v v hys logic hysteresis voltage 0 .2 0.4 0.8 v fan3268tmx_f085 (automotive - qualified versions) v il inx logic low threshold ( 12) 0 .8 1.2 v v ih inx logic high threshold ( 12) 1 .6 2.0 v v hys logic hysteresis voltage ( 12) 0. 1 0 .4 0.8 v continued on the following page? www.onsemi.com 6
fan32 68 ? 2 a low - voltage pmos - nmos bridge driver electrical characteristics (continued) unless otherwise noted, v dd =12 v and t j =- 40c to + 12 5c. currents are defined as positive into the device and negative out of the device. symbol parameter conditions min. typ. max. unit enable v enl enable logic low threshold en from 5 v to 0 v 0.8 1.2 v v enh enable logic high threshold en from 0 v to 5 v 1.6 2 .0 v v hys logic hysteresis voltage ( 10) 0.4 v r pu enable pull - up resistance ( 10) 100 k output i sink out current, mid - voltage, sinking ( 10) o ut at v dd /2, c load =0.1 f, f=1 khz 2.4 a i source out current, mid - voltage, sourcing ( 10) o ut at v dd /2, c load =0.1 f, f=1 khz -1 .6 a i pk_sink out current, peak, sinking ( 10) c load =0.1 f, f=1 khz 3 a i pk_source out current, peak, sourcing ( 10 ) c load =0.1 f, f=1 khz -3 a t rise output rise time ( 11) c load =1000 pf 12 2 2 ns t fall output fall time ( 11) c load = 1000 pf 9 17 ns fan3268t t d1 propagation delay ( 11 ) 0 - 5 v in , 1 v/ns slew rate 7 14 25 ns t d2 propagation delay ( 11) 0 - 5 v in , 1 v/ns slew rate 10 19 34 ns fan3268tmx_f085 (automotive - qualified versions) t d1 propagation delay ( 11 )( 12) 0 - 5 v in , 1 v/ns slew rate 7 14 32 ns t d2 propagation delay ( 11 ) ( 12 ) 0 - 5 v in , 1 v/ns slew rate 8 19 34 ns v oh high level output voltage ( 12) v oh = v dd C v out , i out = C 1 ma 15 40 mv v ol low level output voltage ( 12) i out =1 ma 10 25 mv notes: 9. en inputs have ttl thresholds; refer to the enable section. 10. not tested in production. 11. see the timing diagrams of figure 4 and figure 5 . 12. ap ply only to automotive version(fan32 68tmx_f085) timing diagrams 90% 10% output input or enable t d1 t d2 t rise t fall v inl v inh 90% 10% output t d2 t d1 t fall t rise v inl v inh input or enable figure 4. non - i nverting figure 5. inverting www.onsemi.com 7
fan32 68 ? 2 a low - voltage pmos - nmos bridge driver typical performance characteri stics typical characteristics are provided at t a = 25c and v dd =12 v unless otherwise noted. figure 6. i dd (static) vs. supply voltage ( 13) figure 7. i dd (no - load) vs. frequency figure 8. i dd (1 nf load) vs. frequency figure 9. i dd (static) vs. tempe rature ( 13) figure 10. input thresholds vs. supply voltage figure 11. input thresholds vs. temperature www.onsemi.com 8
fan32 68 ? 2 a low - voltage pmos - nmos bridge driver typical performance characteri stics typical characteristics are provided at t a = 25c and v dd =12 v unless otherwise noted. figure 12. uvlo threshold vs. temperature figure 13. propagation delays vs. supply voltage figure 14. propagation delays vs. supply voltage figure 15. propaga tion delays vs. temperature figure 16. propagation delays vs. temperature www.onsemi.com 9
fan32 68 ? 2 a low - voltage pmos - nmos bridge driver typical performance characteri stics typical characteristics are provided at t a = 25c and v dd =12 v unless otherwise noted. figure 17. fall time vs. supply voltage figure 18. rise time vs. supply voltage figure 19. rise and fall times vs. temperature figure 20. rise/fall waveforms with 1 nf load figure 21. rise/fall waveforms with 10 nf load www.onsemi.com 10
fan32 68 ? 2 a low - voltage pmos - nmos bridge driver typical performance characteri stics typical characteristics are provided at t a = 25c and v dd =12 v unless otherwise noted. figure 22. q uasi - static source current with v dd =12 v figure 23. quasi - static sink current with v dd =12 v figure 24. quasi - static source current with v dd =8 v figure 25. quasi - static sink current with v dd =8 v note: 13. for any inverting inputs pulled low, non - inverting inputs pulled high, or outputs driven high, static i dd increases by the current flowing through the corresponding pull - up/down resistor shown in the block diagram in figure 3 . test circuit 120f al. el. v dd v out 1f ceramic 4.7f ceramic c load 0.1f i out in 1khz current probe lecroy ap015 figure 26. quasi -static i out / v out test circui t www.onsemi.com 11
fan32 68 ? 2 a low - voltage pmos - nmos bridge driver applications information input thresholds the fan3268 driver has ttl input thresholds and provides buffer and level translation functions from logic inputs. the input thresholds meet industry - standard ttl - logic thresholds , independent of the v dd voltag e, and there is a hysteresis voltage of approximately 0.4 v. these levels permit the inputs to be driven from a range of input logic signal levels for which a voltage over 2 v is considered logic high. the driving signal for the ttl inputs should have fast rising and falling edges with a slew rate of 6 v/s or faster, so a rise time from 0 to 3.3 v should be 550 ns or less. with reduced slew rate, circuit noise could cause the driver input voltage to exceed the hysteresis voltage and retrigger the driver in put, causing erratic operation. static supply current in the i dd (static) typical performance characteristics (see figure 6 ) , the curve is produced with all inputs / enables floating (out is low) and indicates t he lowest static i dd current for the tested configuration. for other states, additional current flows through the 100 k ? resistors on the inputs and outputs shown in the block diagram ( see figure 3 ) . in these ca ses, the actual static i dd current is the value obtained from the curves plus this additional current. millerdrive? gate drive technology fan3268 gate drivers incorporate the millerdrive? architecture shown in fi gure 1 . for the output stage, a combination of bipolar and mos devices provide large currents over a wide range of supply voltage and temperature variations. the bipolar devices carry the bulk of the current as out swings betw een one and two thirds v dd and the mos devices pull the output to the high or low rail. the purpose of the millerdrive? architecture is to speed up switching by providing high current during the miller plateau region when the gate - drain capacitance of the mosfet is being charged or discharged as part of the turn - on / turn- off process. for ap plications with zero voltage switching during the mosfet turn - on or turn- off interval, the driver supplies high peak current for fast switching even though the miller plateau is not present. this situation often occurs in synchronous rectifier applications because the body diode is generally conducting before the mosfet is switched on. the output pin slew rate is determined by v dd voltage and the load on the output. it is not user adjustable, but a series resistor can be added if a slower rise or fall time at the mosfet gate is needed. input stage v dd v out f igure 27. millerdrive? output architecture under - voltage lockout internal circuitry provides an under - voltage lockout function that prevents the output switching devices from operating if the v dd supply vo ltage is below the operating level. when v dd is rising, bu t below the 3.9 v operational level, internal 100 k ? resistors bias the non - inverting output low and the inverting output to v dd to keep the external mosfets off during startup intervals when logic control signals may not be present . after the part is active, the supply voltage must drop 0.2 v before the part shuts down. this hysteresis helps prevent chatter when low v dd supply voltages have noise from the power switching. v dd bypass capacitor guidel ines to enable this ic to turn a device on quickly, a local high - frequency bypass capacitor c byp with low esr and esl should be connected between the vdd and gnd pins with minimal trace length. this capacitor is in addition to bulk electrolytic capacitance of 10 f to 47 f commonly found on driver and controller bias circuits. a typical criterion for choosing the value of c byp is to keep the ripple voltage on the v dd supply to 5%. this is often achieved with a value 20 times the equivalent load capacitance c eqv , defined here as q gate /v dd . ceramic capacitors of 0.1 f to 1 f or larger are common choices, as are dielectrics, such as x5r and x7r , with good temperature characteristics and high pulse current capability. if circuit noise affects normal operat ion, the value of c byp may be increased to 50 - 100 times the c eqv or c byp may be split into two capacitors. one should be a larger value, based on equivalent load capacitance, and the other a smaller value, such as 1 -10 nf mounted closest to the vdd and gnd pins to carry the higher frequency components of the current pulses. the bypass capacitor must provide the pulsed current from both of the driver channels and, if the drivers are switching simultaneously, the combined peak current sourced from the c byp wo uld be twice as large as when a single channel is switching. www.onsemi.com 12
fan32 68 ? 2 a low - voltage pmos - nmos bridge driver layout and connection guidelines the fan3268 gate driver incorporates fast - reacting input circuits, short propagation delays, and powerful output stages capable of delivering current peaks ove r 2 a to facilitate voltage transition times from under 10ns to over 150 ns. the following layout and connection guidelines are strongly recommended: ? keep high - current output and power ground paths separate from l ogic and enable input signals and signal ground paths. this is especially critical when dealing with ttl - level logic thresholds at driver inputs and enable pins. ? keep the driver as close to the load as possible to minimize the length of high - current traces. this reduces the series inductance to improve high - speed switching, while reducing the loop area that can radiate emi to the driver inputs and surrounding circuitry. ? if the inputs to a channel are not externally connected, the internal 100 k ? resistors indicated on block diagrams command a low output (channel a) or a high output (channel b). in noisy environments, it may be necessary to tie inputs or enables of an unused channel to vdd or gnd using short traces to prevent noise from causing s purious output switching. ? many high - speed power circuits can be susceptible to noise injected from their own output or other external sources, possibly causing output re - triggering. these effects can be obvious if the circuit is tested in breadboard or non - optimal circuit layouts with long input, enable, or output leads. for best results, make connections to all pins as short and direct as possible. ? the turn - on and turn- off current paths should be minimized. operational waveforms figure 28 shows startup waveforms for non - inverting channel a. at power - up, the driver output for channel a remains low until the v dd voltage reaches the uvlo turn - on threshold, then outa operates in - phase with ina. vdd ina outa uvlo turn-on threshold fi gure 28. non - inverting startu p waveforms figure 29 illustrates startup waveforms for inverting channel b. at power - up, the driver output for channel b is tied to v dd through an internal 100 k resistor until the v dd voltage reaches the uvlo turn - on threshold, then outb operates out of phase with inb. vdd inb outb uvlo turn-on threshold fi gure 29. inverting start u p waveforms www.onsemi.com 13
fan32 68 ? 2 a low - voltage pmos - nmos bridge driver thermal guidelines gate drivers used to switch mosfets and igbts at high frequenci es can dissipate significant amounts of power. it is important to determine the driver power dissipation and the resulting junction temperature in the application to ensure that the part is operating within acceptable temperature limits. the total power d issipation in a gate driver is the sum of two components, p gate and p dynamic : p total =p gate + p dynamic (1) gate driving loss: the most significant power loss results from supplying gate current (charge per unit time) t o switch the load mosfet on and off at the switching frequency. the power dissipation that results from driving a mosfet at a specified gate - source voltage, v gs , with gate charge, q g , at switching frequency, f sw , is determined by: p gate =q g ? v gs ? f sw ? n (2) where n is the number of driver channels in use (1 or 2). dynamic pre - drive / shoot - through current: a power loss resulting from internal current consumption under dynamic operating conditions, including pin pu ll- up / pull - down resistors, can be obtained using the ?i dd (no - load) vs. frequency? graphs in typical performance characteristics to determine the current i dynamic drawn from v dd under actual operating conditions: p dynamic =i dynamic ? v dd ? n (3) once the power dissipated in the driver is determined, the driver junction rise with respect to circuit board can be evaluated using the following thermal equation, assuming www.onsemi.com 14
fan32 68 ? 2 a low - voltage pmos - nmos bridge driver t able 1. related products part number type gate drive ( 14) (sink/src) input threshold logic package FAN3111C single 1 a +1.1 a / - 0.9 a cmos single channel of dual - input/single - output sot23 - 5, mlp6 fan3111e single 1 a +1.1 a / - 0.9 a external ( 15) single non - inverting channel with external reference sot23 - 5, mlp6 fan3100c single 2 a +2.5 a / - 1.8 a cmos single channel of two - input/one - output sot23 - 5, mlp6 fan3100t single 2 a +2.5 a / - 1.8 a ttl single channel of two - input/one - output sot23 - 5, mlp6 fan3226c dual 2 a +2.4 a / - 1.6 a cmos dual inverting channels + dual enable soic8, mlp8 fan3226t dual 2 a +2.4 a / - 1.6 a ttl dual inverting channels + dual enable soic8, mlp8 fan3227c dual 2 a +2.4 a / - 1.6 a cmos dual non - inverting channels + dual enable soic8, mlp8 fan32 27t dual 2 a +2.4 a / - 1.6 a ttl dual non - inverting channels + dual enable soic8, mlp8 fan3228c dual 2 a +2.4 a / - 1.6 a cmos dual channels of two - input/one - output, pin config.1 soic8, mlp8 fan3228t dual 2 a +2.4 a / - 1.6 a ttl dual channels of two - input/one - output, pin config.1 soic8, mlp8 fan3229c dual 2 a +2.4 a / - 1.6 a cmos dual channels of two - input/one - output, pin config.2 soic8, mlp8 fan3229t dual 2 a +2.4 a / - 1.6 a ttl dual channels of two - input/one - output, pin config.2 soic8, mlp8 fan3268t d ual 2 a +2.4 a / - 1.6 a ttl non - inverting channel (nmos) and inverting channel (pmos) + dual enables soic8 fan3223c dual 4 a +4.3 a / - 2.8 a cmos dual inverting channels + dual enable soic8, mlp8 fan3223t dual 4 a +4.3 a / - 2.8 a ttl dual inverting channels + dual enable soic8, mlp8 fan3224c dual 4 a +4.3 a / - 2.8 a cmos dual non - inverting channels + dual enable soic8, mlp8 fan3224t dual 4 a +4.3 a / - 2.8 a ttl dual non - inverting channels + dual enable soic8, mlp8 fan3225c dua l 4 a +4.3 a / - 2.8 a cmos dual channels of two - input/one - output soic8, mlp8 fan3225t dual 4 a +4.3 a / - 2.8 a ttl dual channels of two - input/one - output soic8, mlp8 fan3121c single 9 a +9.7 a / - 7.1 a cmos single inverting channel + enable soic8, mlp8 f an3121t single 9 a +9.7 a / - 7.1 a ttl single inverting channel + enable soic8, mlp8 fan3122t single 9 a +9.7 a / - 7.1 a cmos single non - inverting channel + enable soic8, mlp8 fan3122c single 9 a +9.7 a / - 7.1 a ttl single non - inverting channel + enable soic8, mlp8 note s: 14. typical currents with out at 6 v and v dd = 12 v. 15. thresholds proportional to an externally supplied reference voltage. www.onsemi.com 15
fan32 68 ? 2 a low - voltage pmos - nmos bridge driver physical dimensions 8 0 see detail a notes: unless otherwise specified a) this package conforms to jedec ms-012, variation aa. b) all dimensions are in millimeters. c) dimensions do not include mold flash or burrs. d) landpattern standard: soic127p600x175-8m. e) drawing filename: m08arev15 land pattern recommendation seating plane c gage plane x 45 detail a scale: 2:1 pin one indicator 4 8 1 b 5 a 5.60 0.65 1.75 1.27 6.000.20 3.900.10 4.900.10 1.27 0.420.09 0.1750.75 1.75 max 0.36 (0.86) r0.10 r0.10 0.650.25 (1.04) option a - bevel edge option b - no bevel edge 0.25 c b a 0.10 0.220.30 (0.635) figure 30. 8-l ead small outline integrat ed circuit (soic) www.onsemi.com 16
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